The present invention relates generally to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a tungsten film with low resistivity and low surface roughness and a method for forming the wiring of a semiconductor device using the same.
A wiring in a semiconductor device, e.g. a gate, is formed mainly of a polysilicon film. The polysilicon film is used because it sufficiently satisfies the physical properties required for a gate in a semiconductor device, such as a high melting point, ease of forming a thin film, ease of patterning a line, stability in an oxidation atmosphere, and formation of a planarized surface. Additionally, in a MOSFET device, a low gate resistance can be realized by doping a dopant such as phosphorous (P), arsenic (As), or boron (B) into the polysilicon gate.
However, as the level of integration in a semiconductor device increases, the line width of the gate, the thickness of a gate insulation film, and a junction depth are reduced. These reductions make it difficult to realize the required low resistance in the gate made of polysilicon.
Accordingly, it has become necessary to develop a novel gate material that can replace the polysilicon film. In the early stages of development, a metal silicide film was employed as a gate material, and a polycide gate formed of a stacked structure of the polysilicon film and the metal silicide film was developed. However, the polycide gate also reached limitations in realizing the low resistance required in a semiconductor device of sub-100 nm technology.
Therefore, recent developments have gone in the direction of a metal gate formed of a stacked structure of the polysilicon film and a metal film. The metal gate does not use a dopant, and thus it is possible to solve the problems generated in the polycide gate. Also, the metal used in the metal film has a work function value corresponding to the mid band-gap of silicon, making it possible to apply the metal film as a single gate that can be used simultaneously in both a NMOS area and a PMOS area. For example, a tungsten gate that employs tungsten is being actively studied.
However, a problem still exists when using tungsten as the gate material, in that an increase in gate resistance has been caused by: a decrease in a gate critical dimension; a line width effect; and an increase in the tungsten resistivity. Accordingly, studies have been conducted to solve the problem of the increased gate resistance resulting from the increase in the tungsten resistivity. Many unsuccessful attempts were made to solve the problem of increased gate resistance with any type of satisfaction, until now.